The present invention is directed to parallel plate capacitors as well as decoupling capacitors for semiconductor applications. More specifically, the invention is directed to discrete, low inductance capacitors typically used in decoupling applications.
The purpose of power distribution systems is to deliver stable, noise-free power to integrated circuits (ICs) and other devices. One way to express this quantitatively is that the power distribution impedance, as seen from a chip, must be less than some value, over whatever frequency range is of interest. The value is determined by the voltage drop or noise tolerance of the chip when it is drawing maximum current. For example, simply considering the DC drop allowed for a chip drawing 5 A from a 5 V supply with a 5% voltage tolerance, the total power distribution impedance seen by the chip must be less than 50 mxcexa9. For AC noise, time domain equivalent circuit simulations are usually performed, since a wide range of frequencies is generated by digital circuitry. Simultaneous switching drivers generate di/dt noise, as has been exhaustively described elsewhere by H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Chapter 7, Addison-Wesley, 1990, incorporated herein by reference.
Capacitors have been used for decoupling, or bypassing AC noise on DC power supply circuits for many years. These capacitors can be thought of as supplying localized energy storage for the varying current demands of circuitry, typically semiconductor circuits, and thus stabilizing the DC power.
At low frequencies, almost all capacitors are effective to decouple AC signals. Usually several capacitors are used on a printed circuit board to provide a very low impedance path for AC signals, while maintaining DC isolation. For example, tantalum electrolytic capacitors of 10 to 100 xcexcF might be used to provide maximum energy storage and low frequency decoupling for an entire circuit board, while ceramic chip capacitors of 0.1 xcexcF might be located next to every integrated circuit to provide a local path for grounding high frequency noise.
Such distributed capacitance schemes worked well when the clock frequencies of digital systems were relatively low, such as 10 to 20 MHz. However, as clock frequencies have increased to above 100 MHz, conventional capacitors are limited. The problem is that in reality, capacitors also exhibit inductance and resistance components, and this inductance becomes a problem at higher frequencies.
In that regard, a capacitor can be modeled as a series RLC circuit. The inductance is present because of the finite dimensions of the plates and the way in which the plates are connected to the remainder of a circuit, the later exerting a major influence at the higher frequencies. The limited dimensions of the conductors connecting the plates to the remainder of the circuit impart finite, though small, inductances. Even in capacitors of moderate sizes, the resulting inductance-capacitance (LC) combination can resonate at a fairly low frequency. For example, the typical 0.1 xcexcF ceramic chip capacitor (measuring 0.12 inch by 0.06 inch) has a self-inductance of approximately 500 pH and is self resonant around 20 MHz. From DC to around 20 MHz, the impedance decreases down to a level of 150 mOhms, but above 20 MHz, the impedance increases, and the capacitor loses its decoupling effectiveness. Stated in these terms, the capacitor can be thought of as a four terminal device, whose function is to prevent AC disturbance imposed on one set of terminals from being coupled to the other set of terminals. In microwave terms, this two port network must have a high insertion loss (S12)between the two ports, to be effective.
Also detrimental to effective decoupling is the inductance between the IC (integrated circuit) chip itself and the printed circuit wiring board power distribution planes to which the decoupling capacitors are connected. This inductance arises from the leads of the chip package. Connecting many leads in parallel to power and ground connections does not totally eliminate this effect.
If large current swings are required by the IC circuitry, this residual inductance can cause unacceptable voltage drops and AC noise. To counteract this effect, decoupling capacitors have been included in IC circuit packages, often as discrete chip components, but sometimes as multiple planes with thin dielectric layers between them, which in effect form integral capacitors. This latter arrangement is particularly effective in multilayer ceramic packages such as pin grid arrays (PGAs), quad flat packs (QFPs) and ball grid arrays (BGAs).
In multichip modules (MCMs), the effect of the inductances of chip-to-substrate interconnections can be minimized by using multiple interconnections and careful design both in a wirebond and in a flip chip environment. Similarly, the intrinsic inductance and resistance of power distribution planes, either solid, perforated, or the new IMPS (interconnected mesh power system), is extremely low, and does not determine the effectiveness of power distribution. My prior U.S. Pat. No. 5,410,107 describes the IMPS.
Thus discrete decoupling capacitors are critical elements for reducing power distribution noise.
In MCM applications, there are three inductances to consider: interconnects between chip and substrate, substrate power and ground planes, and the inductance of the capacitor itself, including its connection to the power and ground planes.
It has long been known that the least inductive capacitor is a parallel plate capacitor with a large area. The ultimate low-inductance capacitor in MCM substrates is the parallel plate capacitor consisting of a thin layer of high dielectric constant material sandwiched between power and ground planes. However, these capacitors are expensive to fabricate and contribute significantly to substrate defects. The need to distribute multiple voltages (e.g., 3.3 V, 5 V, etc.) makes their use prohibitive in many applications.
In an earlier patent of mine, U.S. Pat. No. 4,675,717, there is described such a capacitor in the context of a wafer-scale integrated (WSI) assembly, built on silicon substrates, in which the conductive silicon substrate forms the ground plate of the capacitor and allows the easy growth of a silicon dioxide dielectric layer. A metal layer formed over the dielectric layer serves as the other plate of the capacitor, in addition to serving as the power distribution plane. Such integrated power distribution and decoupling capacitor combinations have demonstrated low impedance characteristics without inductive resonances to tens of gigahertz. But again, such structures are expensive to produce, and do not work with many sets of packaging materials. Discrete capacitors are still required to handle the vast majority of decoupling applications.
Various manufacturers have made progress on reducing the inductance of discrete capacitors.
One such manufacturer, AVX Corporation, produces low-inductance capacitor arrays, designed in conjunction with IBM, in which multiple connections to the plates are made along one side of the unit or part, using solder bumps or thermocompression gold ball bonding. See, J. Galvagni, xe2x80x9cLow Inductance Capacitors For Digital Computers,xe2x80x9d AVX Technical Information brochure, and AVX Corporation product brochure entitled xe2x80x9cLow Inductance Capacitor Arrays,xe2x80x9d incorporated herein by reference. Such capacitors are made available under the designation AVX LICAxe2x80x94Low Inductance Decoupling Capacitor Arrays as an extension to IBM Corp.""s DCAP(copyright) decoupling capacitors. The AVX LICA are available in values from 30 to 150 nF. Custom designs incorporating multiple sections can be produced. Testing of these devices results in measurements of total inductance below 60 pH.
Another manufacturer, Murata, produces a very small capacitor (20xc3x9720xc3x9713 mil) having a capacitance of 10 or 2.2 nF. The contacts are on opposite 20 mil square faces. Though originally designed to be mounted with one face down and the other face wirebonded, it is possible to obtain even lower inductance by mounting the part with both terminals perpendicular to the plane of a substrate.
H. Hashimi and P. Sandborn have described what is referred to as a close attached capacitor (CAC) which is a unit that is mounted directly on the active area of an IC chip, and wirebonded to chip power and ground pads, to overcome inductance in the unit. See, H. Hashemi and P. Sandborn, xe2x80x9cThe Close Attached Capacitor: A solution to Switching Noise Problems,xe2x80x9d Proceedings of the 42 nd ECTC, 1992, pp. 573-582, incorporated herein by reference. Unfortunately, the wirebond connections are still significantly inductive, and the silicon-based capacitors are expensive.
Along other lines, there has been under development an integrated capacitor layer for printed wiring boards to simultaneously create many capacitors for radio frequency (RF) circuit applications as a replacement for discrete chip components. This layer uses patterned metal as a set of floating plates underneath an unpatterned deposited dielectric, above which a set of patterned metal plates including terminal pads is formed.
The present invention provides a new and novel capacitor structure and method for making same. The capacitor comprises an extremely low inductance floating plate capacitor which can be fabricated with as little as one patterning step. These devices can be fabricated in large quantity on sheet or roll material and subsequently excised by cutting or stamping.
These capacitors preferably are used in decoupling applications, which applications can advantageously utilize the low-inductance nature of the floating plate capacitor and its method of attachement. The extremely high insertion loss, i.e., decoupling effectiveness, of these capacitors is maintained at frequencies exceeding 1 GHz, even over a wide band from about 1 GHz to 10 GHz.
In an embodiment, the invention provides a capacitor which does not exhibit a significant increase in impedance with increasing frequency.
In an embodiment, the invention provides a capacitor which exhibits an average insertion loss of at least xe2x88x9240 dB at frequencies above 1 GHz.
In an embodiment, the invention provides a capacitor comprising a floating plate electrode, at least two patterned plate electrodes overlying the floating plate electrode, and a dielectric layer therebetween.
In an embodiment, the capacitor is effective to exhibit an insertion loss of at least xe2x88x9240 dB at frequencies from 1 to about 10 GHz.
In an embodiment, the floating plate electrode consists of a metal film (preferably aluminum or Tixe2x80x94Cu) with a thickness of about 1000 xc3x85 to about 1 xcexcm.
In an embodiment, the dielectric layer is selected from the group consisting of barium titanate, tantalum oxide, aluminum oxide, organic dielectrics and inorganic dielectrics.
In an embodiment, the dielectric layer is from about 2000 xc3x85 to about 1 xcexcm thick.
In an embodiment, the at least two patterned plate electrodes are selected from the group consisting of metals, conductive inks and conductive pastes.
In an embodiment, the patterned plates comprise electroforms.
In an embodiment the invention provides an insulating layer or substrate on a face of the floating plate electrode opposite the at least two patterned plate electrodes.
In an embodiment, the insulating substrate is selected from the group consisting of oxidized metal, ceramic, silicon, glass and polymer.
In an embodiment, the invention provides a method of forming a capacitor comprising:
a) forming a floating plate electrode;
b) forming a dielectric layer over the floating plate electrode; and
c) forming at least two patterned plate electrodes on the dielectric layer in overlying relationship with respect to the floating plate electrode.
In an embodiment the invention provides a method of forming a capacitor comprising:
a) providing a metallic layer;
b) providing a dielectric layer on one face of the metallic layer; and
c) providing at least one pair of patterned electrodes on the dielectric layer on a side of the dielectric layer opposite the metallic layer.
In an embodiment, the invention further includes providing an insulating layer on a face of the metallic layer opposite the dielectric layer.
In an embodiment, the providing of the metallic layer with an insulating layer comprises providing a metallic layer and then oxidizing one side of the metallic layer until a sufficiently electrically insulating layer is formed.
In an embodiment, the metallic layer is aluminum.
In an embodiment, the metallic layer is a sheet of aluminum foil.
In an embodiment, the dielectric layer comprises barium titanate, tantalum oxide, aluminum oxide, an organic dielectric or an inorganic dielectric.
In an embodiment, the providing of the patterned plates can comprise sputtering plates onto the dielectric layer, photolithographically defining a metal, such as copper, onto the dielectric layer, screen printing a conductive ink or paste onto the dielectric layer, or electroplating an electroform in the dielectric layer.
In an embodiment, the providing of the metallic layer comprises providing a rollform metallic material.
In an embodiment, the providing of an insulating layer comprises applying an insulating layer to the rollform metallic material, e.g., by lamination, oxidation or other suitable application.
In an embodiment, a polymer sheet is coated with a metallic layer to provide the insulating layer and metallic layer, respectively.
These and other features and aspects of the invention are presented below with reference to the drawings in the following detailed description of the presently preferred embodiments.